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| INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 TOSHIBA RISC PROCESSOR TMPR4927ATB-200 (64-bit RISC MICROPROCESSOR) 1. GENERAL DESCRIPTION The TMPR4927ATB, to be referred as TX4927 MIPS RISC micro-controller is a highly integrated ASSP solution based on Toshiba's TX49/H2 processor core, a 64-bit MIPS I,II,III ISA Instruction Set Architecture (ISA) compatible with additional instructions. The TX4927 is a highly integrated device with integrated peripherals such as SDRAM memory controller, PCI controller, PIO, AC-Link, UART and Timer. This class of product is targeted for applications that require a high performance and cost-effective solution such as networking and printers. 2. FEATURES * * * * * * * * * * TX49/H2 core with an integrated IEEE 754-compliant FPU for single- / double-precision operations 4-channel SDRAM Controller ( 64-bit 100MHz ) 8-channel External Bus Controller 32-bit PCI Controller ( 32-bit 33 / 66 MHz ) 4-channel Direct Memory Access ( DMA ) Controller 2-channel Serial I/O Port Parallel I/O Port (up to 16-bit) 3-channel Timer / Counter AC-Link ( AC97 Interface ) Low power dissipation ( Typ. 1.5 W ) The TX4927 operates with the 1.5V Int. and the 3.3V I/O, while supporting a low-power ( Halt ) mode. * CPU maximum operating frequency: 200 MHz * IEEE1149.1 (JTAG) support: Debug Support Unit ( Enhanced JTAG ) * 420-pin TBGA *The information contained herein is subject to change without notice. *TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. * EJC-TMPR4927ATB-1 17 / Jan / 02 TOSHIBA CORPORATION INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 2.1 Internal Block Diagram Figure 1 shows the TX4927 internal block diagram. Clock Generator ( PLL ) Debug (DSU) G D$(32K) SDRAMC I B U S 64bit Gbus IU MMU I$(32K) DMAC External BUS Controller External BUS Interface PCIC GPR MAC BIU WB FPU TX49/H2 CPU Core IM bus IM bus bridge ACLC UART Timer PIO IRC Figure 1 TX4927 Internal Block Diagram EJC-TMPR4927ATB-2 17 / Jan / 02 TOSHIBA CORPORATION INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 2.2 System Block Diagram Figure 2 shows the system block diagram with TX4927. PLL 64bit Gbus SDRAMC G I B U S DMAC External BUS Controller External BUS Interface PCIC Debug (DSU) D$(32K) GPR MAC IU MMU WB FPU I$(32K) BIU SDRAM Control signals SDRAM Memory Devices External System Bus ( Data : 64bit, Address : 20bit ) TX49/H2 CPU Core Control Signals IM bus IM bus bridge ROM/ Flash/ SRAM Ext. I/O Dev. ACLC UART Timer PIO IRC 32 PCI Bus PCI Devices User logic PCIC Figure 2 Typical TX4927 System Block Diagram EJC-TMPR4927ATB-3 17 / Jan / 02 TOSHIBA CORPORATION INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 2.3 TX49/H2 Core Block Diagram Figure 3 shows the internal block diagram of the TX49/H2 core TX49/H2 Core Integer Unit GPR Data Path MAC FPU Pipeline Control CP0 CP0 Registers MMU/TLB Exception Unit CP1 Debug Support Unit 32KB 4-way set Instruction Cache Write Buffer 32KB 4-way set Data Cache Figure 3 TX49/H2 Core Block Diagram 2.4 TX49/H2 CORE FEATURES The TX49/H2 Core is high performance and low-power 64-bit RISC processor core developed by Toshiba. * * * * * * * * * * 64-bit operation 32, 64-bit integer general purpose registers 32-bit physical address space and 64-bit virtual address space Optimized 5-stage pipeline Instruction Set MIPS I, II , III compatible ISA PREF (Prefetch) and MAC (Multiply/Accumulate) instructions. 32k Byte Instruction Cache, and 32k Byte Data Cache 4-way set associative with lock function MMU (Memory Management Unit): 48-entry fully associative JTLB The on-chip FPU supports both single- and double-precision arithmetic, as specified in IEEE Std 754. On-chip 4-deep write buffer Enhanced JTAG debug feature Built-in Debug Support Unit (DSU) EJC-TMPR4927ATB-4 17 / Jan / 02 TOSHIBA CORPORATION INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 2.5 TX4927 Peripheral Circuit FEATURES n External Bus Controller ( EBUSC ) The External Bus Controller generates necessary signals to control external memory and I/O devices. * * * * * * * 8 channels of chip select signals, enabling control of up to eight devices Supports access to ROM ( including mask ROM, page mode ROM, EPROM and EEPROM), SRAM, flash ROM, and I/O devices Supports 32-bit, 16-bit and 8-bit data bus sizing on a per channel basis Supports selection among full speed (uo to 100MHz ), 1/2 speed ( up to 50MHz), 1/3 speed ( uo tp 33MHz ) and 1/4 speed ( up to 25MHz) on a per channel basis Support specification of timing on a per channel basis The user can specify setup and hold times for address, chip enable, write enable, and output enable signals Supports memory sizes of 1M byte to 1G byte for devices with 32-bit data bus, 1M byte to 512M bytes for devices with 16-bit data bus, and 1M byte to 256M bytes for devices with 8-bit data bus n DMA Controller ( DMAC ) The TX4927 contains a 4-channel DMA controller that executes DMA transfer to memory and I/O devices. * * * * * * * * 4-channel independently handling internal / external DMA requests Supports DMA transfer with built-in serial I/O controller and AC-link controller based on internal DMA requests Supports signal address ( fly-by DMA ) and dual address transfers in external I/O DMA transfer mode using external DMA requests Supports transfer between memory and external I/O devices having 32 / 16 / 8-bit data bus Supports memory-to-memory copy mode, with no address boundary restrictions Supports burst transfer of up to 8 double words for a single read / write Supports memory fill mode, writing double-word data to specified memory area Supports chained DMA transfer EJC-TMPR4927ATB-5 17 / Jan / 02 TOSHIBA CORPORATION INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 n SDRAM Controller ( SDRAMC ) The SDRAM Controller generates necessary control signals for the SDRAM interface. It has four channels and can handle up to 2G bytes ( 512 MB/channel ) of memory by supporting a variety of memory configurations. * * * * * * * * * n Memory clock frequency : 50 to 100MHz 4 sets of independent memory channels Supports 16M / 64M / 128M / 256M-bit SDRAM with 2/4 bank size availability Supports use of Registered DIMM Supports ECC or parity generation / check functions Supports 64 / 32-bit data bus sizing on a per channel basis Supports specification of SDRAM timing on a per channel basis Supports critical word first access of TX49/H2 core Low power mode : selectable between self-refreshing and pre-charge power-down PCI Controller ( PCIC ) The TX4927 contains a PCI Controller that complies with PCI Local Bus Specification Revision 2.2. * * * * * * * Compliance with PCI Local Bus Specification Revision 2.2 32-bit PCI interface featuring maximum PCI bus clock frequency of 66MHz Supports both target and initiator functions Supports change of address mapping between internal bus and PCI bus PCI bus arbiter enables connection of up 4 external bus masters Supports booting of TX4927 from memory on PCI bus 1 channel of DMA controller dedicated to PCI controller ( PDMAC ) n Serial I/O Controller ( UART ) The TX4927 contains a 2-channels asynchronous serial I/O interface ( full duplex UART ). * * * * * * 2-channel full duplex UART Built-in baud rate generator FIFOs 8-bit x 8 transmitter FIFO 13-bit ( 8 data bits and 5 status bits ) x 16 receiver FIFO Supports DMA tranfer EJC-TMPR4927ATB-6 17 / Jan / 02 TOSHIBA CORPORATION INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 n Timers / Counters Controller ( TMR ) The TX4927 contains 3-channel timer / counters. * * * * * 3-channel 32-bit up-counter Supports three modes : interval timer mode, pulse generator mode, and watchdog timer mode 2 timer output pins 1 count clock input pin 1 external watchdog reset signal n Parallel I/O Ports ( PIO ) The TX4927 contains 16-bit parallel I/O ports ( including 8 bits shared with CB [ 7 : 0 ] ). * Independent selection of direction of pins and output port type ( totem-pole or open-drain outputs ) on a per bit basis. n AC-link controller ( ACLC ) The TX4927 contains an AC-link controller, which can be operated using any audio and / or modem CODECs described in Audio CODEC'97 Revision 2.1 ( AC'97 ). * * * * * * * Supports up to two CODECs Supports recording and playback for right and left 16-bit PCM channels Supports playback for 16-bit surround, center, and LFE channels Supports audio recording and layback at variable rate Supports Line1 and GPIO slots for modem CODEC Supports AC-link low power mode, wakeup, and warm reset Supports input / output of sample data by DMA transfer EJC-TMPR4927ATB-7 17 / Jan / 02 TOSHIBA CORPORATION INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 n Interrupt Controller ( IRC ) The TX4927 contains an interrupt controller, which receives interrupt requests sent by both the TX4927's built-in peripherals and external devices and issues interrupt requests to the TX49/H2 core. It has a 16-bit flag register to generate interrupt requests to external devices or the TX49/H2 core. * * * * Supports 18 internal interrupt sources from built-in peripherals and 6 external interrupt signal inputs 8 interrupt priority levels for each interrupt source Supports selection between edge- and level-triggered interrupt detection for each external interrupt 16-bit read / write flag register for interrupt requests, making it possible to issue interrupt request to external devices and to the TX49/H2 core ( IRC interrupts ) n Extended EJTAG Interface The TX4927 contains an Extended Enhanced Joint Test Action Group ( Extended EJTAG ) interface, which provides two functions : JTAG boundary scan test that complies with IEEE1149.1 and real-time debugging using a debug support unit ( DSU ) built into the TX49/H2 core. * * IEEE 1149.1 JTAG Boundary Scan Real-time debugging functions using special emulation probe : execution control ( execution, break, step, and register / memory access ) and PC trace EJC-TMPR4927ATB-8 17 / Jan / 02 TOSHIBA CORPORATION INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 3. Pins 3.1 Pin designations A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 PIO[1] PIO[0] SWE* CE[7]* CE[5]* CE[4]* DMAACK[2] DMAACK[1] BWE[0]* BWE[1]* EEPROM_DI EEPROM_DO Vss EEPROM_SK EEPROM_CS PCST[3] PCST[0] PCIAD[2] PCIAD[5] C_BE[0] PCIAD[11] PCIAD[15] Vss VddIO IRDY* C_BE[2] PIO[3] PIO[2] BUSSPRT* CE[6]* VddIO CE[3]* DMAACK[3] DMAREQ[2] DMAREQ[1] BWE[2]* TCK DCLK TDO PCST[8] PCST[5] PCST[2] B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 PCIAD[0] PCIAD[3] PCIAD[6] PCIAD[8] PCIAD[12] C_BE[1] PERR* STOP* FRAME* Vss PIO[5] PIO[4] VddIO ACK* ACE* CE[2]* CE[1]* DMAREQ[3] VddIO BWE[3]* TDI TMS TPC[3] PCST[7] PCST[4] PCST[1] PCIAD[1] VddIO PCIAD[7] PCIAD[9] PCIAD[13] PAR LOCK* DEVSEL* PCIAD[17] PCIAD[16] PIO[7] Vss PIO[6] VddIN BYPASSPLL* Vss D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 CE[0]* VddIN Vss VddIN DMAACK[0] VddIO TPC[2] VddIO VddIN VddIO VddIN PCIAD[4] VddIO M66EN VddIO SERR* VddIN TRDY* VddIO PCIAD[18] TCLK TIMER[0] TIMER[1] VddIO Vss SDIN[1] VddIO Vss DMADONE* Vss DMAREQ[0] Vss TPC[1] PCST[6] Vss TRST* Vss Vss Vss PCIAD[10] PCIAD[14] Vss E23 E24 E25 E26 F1 F2 F3 F4 F5 F22 F23 F24 F25 F26 G1 G2 G3 G4 G5 G22 G23 G24 G25 G26 H1 H2 H3 H4 H5 H22 H23 H24 H25 H26 J1 J2 J3 J4 J5 J22 J23 J24 PCIAD[22] PCIAD[21] PCIAD[20] PCIAD[19] INT[2] INT[1] INT[0] NMI* VddIN VddIO C_BE[3] ID_SEL VddIO PCIAD[23] INT[5] INT[4] INT[3] RXD[0] VddIN PCIAD[28] PCIAD[27] PCIAD[26] PCIAD[25] PCIAD[24] TXD[0] RTS[0]* CTS[0]* VddIO Vss Vss VddIN PCIAD[29] VddIO PCICLK[0] SCLK TXD[1] RTS[1]* CTS[1]* RXD[1] PCIAD[31] Vss PCIAD[30] J25 J26 K1 K2 K3 K4 K5 K22 K23 K24 K25 K26 L1 L2 L3 L4 L5 L22 L23 L24 L25 L26 M1 M2 M3 M4 M5 M22 M23 M24 M25 M26 N1 N2 N3 N4 N5 N22 N23 N24 N25 N26 GNT[0]* PCICLK[1] RESET* TEST[0]* HALTDOZE VddIN Vss Vss VddIN GNT[1]* REQ[0]* PCICLK[2] SYSCLK TEST[4]* TEST[3]* TEST[2]* TEST[1]* REQ[1]* Vss REQ[2]* GNT[2]* PCICLK[3] OE* WDRST* VddIO VddIN Vss Vss VddIO REQ[3]* GNT[3]* PCICLK[4] DATA[1] DATA[32] DATA[0] Vss VddIO PME* VddIO Vss DATA[63] PCICLK[5] EJC-TMPR4927ATB-9 17 / Jan / 02 TOSHIBA CORPORATION INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 P1 P2 P3 P4 P5 P22 P23 P24 P25 P26 R1 R2 R3 R4 R5 R22 R23 R24 R25 R26 T1 T2 T3 T4 T5 T22 T23 T24 T25 T26 U1 U2 U3 U4 U5 U22 U23 U24 U25 U26 V1 V2 DATA[2] Vss DATA[33] Vss VddIO VddIN CGRESET* PLL2Vcc_A PLL2Vss_A PCICLKIN DATA[35] DATA[3] DATA[34] VddIO Vss Vss VddIN PLL1Vcc_A PLL1Vss_A MASTERCLK Vss DATA[5] DATA[36] VddIO DATA[4] DATA[30] DATA[62] VddIO DATA[31] Vss DATA[38] DATA[6] DATA[37] VddIN Vss Vss VddIN VddIO DATA[61] Vss Vss Vss V3 V4 V5 V22 V23 V24 V25 V26 W1 W2 W3 W4 W5 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y22 Y23 Y24 Y25 Y26 AA1 AA2 AA3 AA4 AA5 AA22 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 VddIO VddIO DATA[7] VddIO DATA[28] Vss DATA[60] DATA[29] DATA[8] DATA[39] Vss VddIN Vss Vss VddIO Vss DATA[27] DATA[59] DATA[10] DATA[41] Vss DATA[9] DATA[40] VddIO DATA[25] DATA[57] DATA[26] DATA[58] DATA[43] DATA[11] VddIO Vss DATA[42] DATA[23] Vss DATA[55] DATA[24] DATA[56] DATA[45] DATA[13] DATA[44] DATA[12] AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 Vss DQM[0] VddIO Vss ADDR[3] Vss ADDR[7] Vss Vss Vss Vss ADDR[17] Vss SDCS[3]* Vss DQM[7] CB[3] Vss VddIO Vss DATA[54] Vss DATA[14] Vss Vss VddIN VddIO Vss SDCS[0]* VddIO VddIO VddIN ADDR[8] VddIN VddIO VddIO VddIO VddIO VddIN DQM[2] VddIN CB[2] AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 Vss DATA[48] VddIN Vss DATA[53] DATA[22] VddIO DATA[46] CB[0] Vss Vss DQM[4] SDCS[1]* Vss Vss ADDR[5] Vss ADDR[10] ADDR[12] ADDR[14] ADDR[15] ADDR[18] CKE DQM[6] Vss Vss CB[7] DATA[17] Vss DATA[50] DATA[52] DATA[21] DATA[15] VddIO CB[4] CB[5] WE* DQM[1] RAS* ADDR[1] ADDR[4] ADDR[6] AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 ADDR[9] Vss ADDR[13] Vss ADDR[16] ADDR[19] SDCS[2]* Vss DQM[3] CB[6] VddIO DATA[49] Vss VddIO DATA[20] VddIO Vss DATA[47] CB[1] CAS* Vss DQM[5] ADDR[0] ADDR[2] VddIO Vss VddIO ADDR[11] SDCLK[2] SDCLK[0] SDCLKIN Vss SDCLK[3] Vss SDCLK[1] VddIO DATA[16] DATA[18] VddIO DATA[19] DATA[51] Vss EJC-TMPR4927ATB-10 17 / Jan / 02 TOSHIBA CORPORATION INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 3.2 Pin layout A 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 B B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 C C26 C25 C24 C23 C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 D D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 E E26 E25 E24 E23 E22 E21 E20 E19 E18 E17 E16 E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 F F26 F25 F24 F23 F22 G G26 G25 G24 G23 G22 H H26 H25 H24 H23 H22 J J26 J25 J24 J23 J22 K K26 K25 K24 K23 K22 L L26 L25 L24 L23 L22 M M26 M25 M24 M23 M22 N N26 N25 N24 N23 N22 F5 F4 F3 F2 F1 G5 G4 G3 G2 G1 H5 H4 H3 H2 H1 J5 J4 J3 J2 J1 K5 K4 K3 K2 K1 L5 L4 L3 L2 L1 M5 M4 M3 M2 M1 N5 N4 N3 N2 N1 EJC-TMPR4927ATB-11 17 / Jan / 02 TOSHIBA CORPORATION INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 P P26 P25 P24 P23 P22 R R26 R25 R24 R23 R22 T T26 T25 T24 T23 T22 U U26 U25 U24 U23 U22 V V26 V25 V24 V23 V22 W W26 W25 W24 W23 W22 Y Y26 Y25 Y24 Y23 Y22 AA AA26 AA25 AA24 AA23 AA22 AB AB26 AB25 AB24 AB23 AB22 AB21 AB20 AB19 AB18 AB17 AB16 AB15 AB14 AB13 AB12 AB11 AB10 AB9 AB8 AB7 AB6 AC AC26 AC25 AC24 AC23 AC22 AC21 AC20 AC19 AC18 AC17 AC16 AC15 AC14 AC13 AC12 AC11 AC10 AC9 AC8 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AD AE AF AF26 AF25 AF24 AF23 AF22 AF21 AF20 AF19 AF18 AF17 AF16 AF15 AF14 AF13 AF12 AF11 AF10 AF9 AF8 AF7 AF6 AF5 AF4 AF3 AF2 AF1 AD26 AE26 AD25 AE25 AD24 AE24 AD23 AE23 AD22 AE22 AD21 AE21 AD20 AE20 AD19 AE19 AD18 AE18 AD17 AE17 AD16 AE16 AD15 AE15 AD14 AE14 AD13 AE13 AD12 AE12 AD11 AE11 AD10 AE10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AE9 AE8 AE7 AE6 AE5 AE4 AE3 AE2 AE1 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 P5 P4 P3 P2 P1 R5 R4 R3 R2 R1 T5 T4 T3 T2 T1 U5 U4 U3 U2 U1 V5 V4 V3 V2 V1 W5 W4 W3 W2 W1 Y5 Y4 Y3 Y2 Y1 AA5 AA4 AA3 AA2 AA1 AB5 AB4 AB3 AB2 AB1 EJC-TMPR4927ATB-12 17 / Jan / 02 TOSHIBA CORPORATION INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 3.3 Pin Description Note: In the I/O columns, "PU" indicates an I/O pin with a pull-up resistor, and the term "OD" indicates an open drain output. * denotes an active-low signal when used as a suffix to a signal name. Signal Name Type Function SDRAM / External Bus Interface Common Signals ADDR[19:0] I/O PU Addresses Address signals. For SDRAM, ADDR[19:5] are used . When the external bus controller uses these pins, the meaning of each bit varies with the data bus width. The ADDR signals are also used as boot configuration signals (input) during a reset. ADDR signals are input signals only when the RESET* signal is asserted and become output signals after the RESET* signal is deasserted. DATA[63:0] I/O PU Data Bus 64-bit data bus. The DATA[15:0] signals are also used as boot configuration signals (input) during a reset. BUSSPRT* O BUS Separate Controls the connection and separation of devices controlled by the external bus controller to or from a high-speed device, such as SDRAM. H: Separate devices other than SDRAM from the data bus. L: Connect devices other than SDRAM to the data bus. Separation and connection are performed using external bi-directional bus buffers (such as the 74xx245). EJC-TMPR4927ATB-13 17 / Jan / 02 TOSHIBA CORPORATION INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 Signal Name Type Function SDRAM Interface Signals SDCLK[3:0] O SDRAM Controller Clock Clock signals used by SDRAM. The clock frequency is the same as the G-Bus clock (GBUSCLK) frequency. When these clock signals are not used, the pins can be set to H using the SDCLK Enable field of the configuration register (CCFG.SDCLKEN[3:0]). SDCLKIN I/O SDRAM feedback clock input Feedback clock signal for SDRAM controller input signals. Setting the SDCLKINEN bit of the pin configuration register causes the TX4927 to feed back signals internally, making SDCLKIN an output signal. CKE O Clock Enable CKE signal for SDRAM. SDCS[3:0]* O Synchronous Memory Device Chip Select Chip select signals for SDRAM. RAS* O Row Address Strobe RAS signal for SDRAM. CAS* O Column Address Strobe CAS signal for SDRAM. WE* O Write Enable WR signal for SDRAM. EJC-TMPR4927ATB-14 17 / Jan / 02 TOSHIBA CORPORATION INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 Signal Name DQM[7:0] Type O Data Mask Function During a read cycle, they control the SDRAM output buffers. The bits correspond to the following data bus signals: DMQ[7] : DATA[63:54], DMQ[6] : DATA[53:48] DMQ[5] : DATA[47:40], DMQ[4] : DATA[39:32] DMQ[3] : DATA[31:24], DMQ[2] : DATA[23:16] DMQ[1] : DATA[15:8], CB[7:0] DMQ[0] : DATA[7:0] I/O PU ECC control or Data parity ECC/parity check bit signals. The bits correspond to the following data bus signals:. CB[7] : DATA[63:54], CB[6] : DATA[53:48] CB[5] : DATA[47:40], CB[4] : DATA[39:32] CB[3] : DATA[31:24], CB[2] : DATA[23:16] CB[1] : DATA[15:8], CB[0] : DATA[7:0] CB[7:0] share pins with the PIO[15:8] signals for parallel I/O. The boot configuration signal on the ADDR[18] pin selects between PIO[15:8] and CB[7:0]. EJC-TMPR4927ATB-15 17 / Jan / 02 TOSHIBA CORPORATION INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 Signal Name Type Function External Bus Interface Signals SYSCLK O System Clock Clock for external I/O devices. Outputs a clock in full speed mode (at the same frequency as the G-Bus clock (GBUSCLK) frequency), half speed mode (at one half the GBUSCLK frequency), third speed mode (at one third the GBUSCLK frequency), or quarter speed mode (at one quarter the GBUSCLK frequency). The boot configuration signals on the ADDR[14:13] pins select which speed mode will be used. When this clock signal is not used, the pin can be set to H using the SYSCLK Enable bit of the configuration register (CCFG.SYSCLKEN). Address Clock Enable Latch enable signal for the high-order address bits of ADDR. Chip Enable Chip select signals for ROM, SRAM, and I/O devices. Output Enable Output enable signal for ROM, SRAM, and I/O devices. Static RAM Write Enable Write enable signal for SRAM and I/O devices. Byte Write Enable / Byte Enable BE[3:0]* indicate valid data position on the data bus DATA[31:0] at both read and write bus operation. In 16-bit bus mode, BE[1:0]* is only used. In 8-bit bus mode, BE[0]* is only used. BWE[3:0]* indicate valid data position on the data bus DATA[31:0] at write bus operation. In 16-bit bus mode, BWE[1:0]* is only used. In 8-bit bus mode, BWE[0]* is only used. The following shows the correspondence between BE[3:0]*/BWE[3:0]* and the data bus. BE[3]* / BWE[3]* : DATA[31:24] BE[1]* / BWE[1]* : DATA[15:8] BE[2]* / BWE[2]* : DATA[23:16] BE[0]* / BWE[0]* : DATA[7:0] The function of these signals can be selected from BE[3:0]* and BWE[3:0]* by using the DATA[5] signal and the EBCCRn and BC registers in the External Bus Controller during boot-mode configuration. Acknowledge Flow control signal. ACE* CE [7:0]* OE* SWE* BWE[3:0]* / BE[3:0]* O O O O O ACK* / READY I/O PU EJC-TMPR4927ATB-16 17 / Jan / 02 TOSHIBA CORPORATION INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 Signal Name DMA Interface DMAREQ[3:0] Type Function I PU DMA Request DMA transfer request signals from an external I/O device. The DMAREQ[2] signal shares the pin with the ACRESET* signal. The boot configuration signal on the ADDR[9] pin selects between DMAREQ[2] and ACRESET*. DMAACK[3:0] O DMA Acknowledge DMA transfer acknowledge signals to an external I/O device. The DMAACK[2] signal shares the pin with the SYNC signal. The boot configuration signal on the ADDR[9] pin selects between DMAACK[2] and SYNC. DMADONE* I/O PU DMA Transfer/Chain Finished DMADONE* is either used as an output signal that reports the termination of DMA transfer or as an input signal that causes DMA transfer to terminate. PCI Interface PCICLK[5:0] O PCI Clock PCI bus clock signals. When these clock signals are not used, the pins can be set to H using the PCICLK Enable field of the pin configuration register (PCFG.PCICLKEN[5:0]). PCICLKIN I PCI feedback clock input PCI feedback clock input. PCIAD[31:0] I/O PCI Address and Data Multiplexed address and data bus. C_BE[3:0] I/O Bus Command and Byte Enable Command and byte enable signals. EJC-TMPR4927ATB-17 17 / Jan / 02 TOSHIBA CORPORATION INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 Signal Name PAR Type I/O Parity Function Even parity signal for PCIAD[31:0] and C_BE[3:0]*. FRAME* I/O Cycle Indicates that bus operation is in progress. IRDY* I/O Initiator ready Indicates that the initiator is ready to complete data transfer. TRDY* I/O Target ready Indicates that the initiator is ready to complete data transfer. STOP* I/O STOP The target sends this signal to the initiator to request termination of data transfer. LOCK* I PCI resource clock Indicates that the PCI bus master is locking (exclusively accessing) a specified memory target on the PCI bus. ID_SEL I Initialization Device select Chip select signal used for configuration access. DEVSEL* I/O Device select The target asserts this signal in response to access from the initiator. REQ[3:2]* I Request PCI bus Signals used by the master to request bus mastership. The boot configuration signal on the DATA[2] pin determines whether the built-in PCI bus arbiter is used. In internal arbiter mode, REQ[3:2]* are PCI bus request input signals. In external arbiter mode, REQ[3:2]* are not used. Because the pins are still placed in the input state, they must be pulled up externally. EJC-TMPR4927ATB-18 17 / Jan / 02 TOSHIBA CORPORATION INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 Signal Name REQ[1]* / INOUT Type I/O / OD Request PCI bus Function Signal used by the master to request bus mastership. The boot configuration signal on the DATA[2] pin determines whether the built-in PCI bus arbiter is used. In internal arbiter mode, this signal is a PCI bus request input signal. In external arbiter mode, this signal is an external interrupt output signal (INTOUT). Request PCI bus Signal used by the master to request bus mastership. The boot configuration signal on the DATA[2] pin determines whether the built-in PCI bus arbiter is used. In internal arbiter mode, this signal is a PCI bus request input signal. In external arbiter mode, this signal is a PCI bus request output signal. REQ[0]* I/O GNT[3:0]* I/O Grant PCI bus Indicates that bus mastership has been granted to the PCI bus master. The boot configuration signal on the DATA[2] pin determines whether the built-in PCI bus arbiter is used. In internal arbiter mode, all of GNT[3:0]* are PCI bus grant output signals. In external arbiter mode, GNT[0]* is a PCI bus grant input signal. Because GNT[3:1]* also become input signals, they must be pulled up externally. PERR* I/O Data Parity Error Indicates a data parity error in a bus cycle other than special cycles. SERR* I/OD System Error Indicates an address parity error, a data parity error in a special cycle, or a fatal error. In host mode, SERR* is an input signal. In satellite mode, SERR* is an open-drain output signal. The mode is determined by the boot configuration signal on the ADDR[19] pin. EJC-TMPR4927ATB-19 17 / Jan / 02 TOSHIBA CORPORATION INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 Signal Name M66EN Type I/O 66MHz clock enable Function 1: Enable 66 MHz operating mode. 0: Disable 66 MHz operating mode. In host mode, M66EN is an input signal. In satellite mode, M66EN is an output signal. The mode is determined by the boot configuration signal on the ADDR[19] pin. PME* I/ OD Power management event PME* indicates the power management mode. In host mode, PME* is an input signal. In satellite mode, PME* is an open-drain output signal. The mode is determined by the boot configuration signal on the ADDR[19] pin. EEPROM data in This is a data input signal from a serial EEPROM for PCI configuration. EEPROM data out This is a data output signal to a serial EEPROM for PCI configuration. EEPROM_DI I PU EEPROM_DO O EEPROM_CS O EEPROM chip select This is a chip select signal for a serial EEPROM for PCI configuration. EEPROM_SK O EEPROM SK This is a clock signal for a serial EEPROM for PCI configuration. Timer Interface TIMER[1:0] O Timer Pulse Width Output Timer output signal. TCLK I PU External Timer Clock Timer input clock. TMR0, TMR1 and TMR2 share this signal. Watchdog Reset Watchdog reset output signal. WDRST* OD EJC-TMPR4927ATB-20 17 / Jan / 02 TOSHIBA CORPORATION INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 Signal Name SIO Interface CTS[1:0]* Type Function I PU SIO Clear to Send CTS signals. SIO Request to Send RTS signals. RTS[1:0]* O RXD[1:0] I PU SIO Receive Data Serial data input signal. SIO Transmit Data Serial data output signal. External Serial Clock Input clock for SIO0 and SIO1. SIO0 and SIO1 share this signal. TXD[1:0] 3state O SCLK I PU PIO Interface PIO[15:8] I/O PU PIO Ports Parallel I/O signals. PIO[15:8] share pins with the SDRAM ECC/parity signals (CB[7:0]). The boot configuration signal on the ADDR[18] pin selects between PIO[15:8] and CB[7:0]. PIO Ports Parallel I/O signals. PIO[4:2] share pins with the AC-link interface signals (SDOUT, SDIN[0], and BITCLK). The boot configuration signal on the ADDR[9] pin selects between PIO[4:2] and AC-link interface signals. PIO[7:0] I/O EJC-TMPR4927ATB-21 17 / Jan / 02 TOSHIBA CORPORATION INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 Signal Name Type Function AC-Link Interface ACRESET* O AC '97 Master H/W Reset ACRESET* shares the pin with the DMAREQ[2] signal. The boot configuration signal on the ADDR[9] pin selects between ACRESET* and DMAREQ[2].PIO[15:8] and CB[7:0]. SYNC O 48 kHz Fixed Rate Sample Sync SYNC shares the pin with the DMAACK[2] signal. The boot configuration signal on the ADDR[9] pin selects between SYNC and DMAACK[2]. SDOUT O Serial, Time Division Multiplexed, AC '97 Output Stream SDOUT shares the pin with the PIO[4] signal. The boot configuration signal on the ADDR[9] pin selects between SDOUT and PIO[4]. SDIN[1] I Serial, Time Division Multiplexed, AC `97 Input Stream SDIN[0] I Serial, Time Division Multiplexed, AC '97 Input Stream SDIN[0] shares the pin with the PIO[3] signal. The boot configuration signal on the ADDR[9] pin selects between SDIN[0] and PIO[3]. BITCLK I Serial, Time Division Multiplexed, AC '97 Input Stream BITCLK shares the pin with the PIO[2] signal. The boot configuration signal on the ADDR[9] pin selects between BITCLK and PIO[2]. Interrupt Signals NMI* I PU Non Mask-able Interrupt Non-Mask-able interrupt input. External Interrupt Requests The external interrupt request signals. INT[5:0] I PU EJC-TMPR4927ATB-22 17 / Jan / 02 TOSHIBA CORPORATION INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 Signal Name Type Function EJTAG Debug Interface TCK I PU JTAG clock input Clock input signal for JTAG. TCK is used to execute JTAG instructions and input/output data. JTAG data input / Debug interrupt input When PC trace mode is not selected, this signal is a JTAG data input signal. It is used to input serial data to JTAG data/instruction registers. When PC trace mode is selected, this signal is an interrupt input signal used to cancel PC trace mode for the debug unit. JTAG data outpur / PC Trace output When PC trace mode is not selected, this signal is a JTAG data output signal. Data is output by means of serial scan. When PC trace mode is selected, this signal outputs the value of the noncontiguous program counter in sync with the debug clock (DCLK). TDI / DINT* I PU TDO / TPC[0] O TPC[3:1] O PC Trace Output TPC[3:1] output the value of the noncontiguous program counter in sync with DCLK. TMS I PU JTAG command TMS mainly controls state transition in the TAP controller state machine. Test Reset Input Asynchronous reset input for the TAP controller and debug support unit. When an EJTAG probe is not connected, this pin must be fixed to low. When connecting an EJTAG probe, prevent floating, for example, by connecting a pull-up resistor. When this signal is de-asserted, G-Bus timeout detection is disabled. TRST* I DCLK O Debug Clock A clock output for a real-time debug system. The timing of a serial monitor bus and PC trace interface signal are all defined by this debug clock DCLK. 3 divide the operation clock of the TMPR4927TB at the time of a serial monitor bus operation. EJC-TMPR4927ATB-23 17 / Jan / 02 TOSHIBA CORPORATION INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 Signal Name PCST[8:0] Type O PC Trace Status Function Output PC trace status information and the mode of the serial monitor bus. Clock Signals MASTERCLK I Master Clock Input Input pin for the TX4927 operating clock. A crystal resonator cannot be connected to this pin because the pin does not contain an oscillator. HALTDOZE O Halt/Doze state output This signal is asserted (High output) when the TX4927 enters Halt or Doze mode. BYPASSPLL* I PLL Reset This pin must be fixed to High. CGRESET* I CG Reset CGRESET* initializes the CG Reset signals RESET* I Reset Reset signal. Test signals TEST[4:0]* I PU Test mode Enable Test pins. These pins must be left open or fixed to High. EJC-TMPR4927ATB-24 17 / Jan / 02 TOSHIBA CORPORATION INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 Signal Name Type Function Power pins and Total pin count PLL1Vdd_A, PLL2Vdd_A, PLL1Vss_A, PLL2Vss_A VddIN - Power and Ground pins to internal PLL circuit. PLL1Vcc_A and PLL2Vcc_A = 1.5V, PLL1_Vss_A and PLL2_Vss_A = GND - Internal Power Pins Power pins at 1.5V VddIO - I/O Power Pins Power pins at 3.3V Vss - Ground Digital ground pins. Vss = 0 V. EJC-TMPR4927ATB-25 17 / Jan / 02 TOSHIBA CORPORATION INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 4. Pin Multiplexing A total of 13 pins of the TX4927 have multiplexed functions. Table 4.1 shows the multiplexed pins. The function of a given pin is selected in various ways, depending on the pin(s) involved. Table 4.2 and Table 4.3 show the setting by booting of TX4927. Table 4.1 Pin Multiplexing Signal name CB[7:0] DMAREQ[2] DMAACK[2] PIO[4:2] Multiplexed Function CB[7:0] / PIO[15:8] DMAREQ[2] / ACRESET* DMAACK[2] / SYNC PIO[4:2] / SDOUT, SDIN[0], BITCLK Table 4.2 Setting by ADDR[18] Signal name CB[7:0] ADDR[18]=0 (Non ECC) I/O PIO[15:8] I/O ADDR[18]=1 (ECC) CB[7:0] Table 4.3 Setting by ADDR[9] Signal name DMAREQ[2] DMAACK[2] PIO[4] PIO[3] PIO[2] ADDR[9]=1 (ACLC) O O O I I ACRESET* SYNC SDOUT SDIN[0] BITCLK I O I/O I/O I/O ADDR[9]=0 (Non ACLC) DMAREQ[2] DMAACK[2] PIO[4] PIO[3] PIO[2] EJC-TMPR4927ATB-26 17 / Jan / 02 TOSHIBA CORPORATION INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 5. ELECTRICAL CHARACTERISTICS 5.1 ABSOLUTE MAXIMUM RATING (*1) PARAMETER Supply voltage (for I/O) Supply voltage (for internal) Input voltage (*2) Storage Temperature Power SYMBOL VddIOMax RATING -0.3 to 3.9 -0.3 to 3.0 -0.3 to VddIO + 0.3V -40 to +125 1.5 (Typ.) UNIT V V V C W VCCIntMax VIN TSTG PD Note) (*1) If LSI is used above the maximum ratings, permanent destruction of LSI can result. In addition, it is desirable to use LSI for normal operation under the recommended condition. If these conditions are exceeded, reliability of LSI may be adversely affected. (*2) The maximum rated V ddIOMax voltage must not be exceeded even at V ddIO + 0.3 volts. 5.2 RECOMMENDED OPERATING CONDITIONS (*3) PARAMETER Supply Voltage I/O Internal Operating Case Temperature (*3) SYMBOL VddIO VddIN Tc CONDITION MIN. 3.1 1.4 0 MAX. 3.5 1.6 70 UNIT V V C Functional operation should be restricted to the recommended operating conditions. Those are the limits under which proper device operation is guaranteed. Therefore, the end product must be designed within the recommended voltage and temperature ranges indicated. EJC-TMPR4927ATB-27 17 / Jan / 02 TOSHIBA CORPORATION INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 5.3 DC CHARACTERISTICS DC Characteristics except for PCI interface (Tc = 0 ~ 70C, VddIO = 3.3V 0.2V, VddIN = 1.5V 0.1V, Vss = 0V) PARAMETER Low-level input voltage High-level input voltage Low-level output current Low-level output current High-level output current High-level output current Low-level input leakage current High-level input leakage current Hi-z output leakage current Operating current (for internal) SYM VIL1 VIH1 IOL1 IOL2 IOL3 IOL4 IOH1 IOH2 IOH3 IOH4 IIL1 IIL2 IIH1 IIH2 IOZ ICCInt CONDITIONS (*1) (*1) (*2) VOL =0.4V (*3) VOL =0.4V (*4) VOL =0.4V (*5) VOL =0.4V (*2) VOH =2.4V (*3) VOH =2.4V (*4) VOH =2.4V (*5) VOH =2.4V (*6) VIN =VSS (*7) VIN =VSS (*8) VIN =VCCIO (*9) VIN =VCCIO (*10) VddIO = 3.3V, VddIN = 1.6V, MASTERCLK=100MHz PClock = 200MHz MIN. -0.3 2.0 8 4 16 8 -10 -200 -10 10 -10 MAX. 0.8 VddIO+0.3 UNIT V V mA mA mA mA mA mA mA mA A A A A A mA -8 -4 -16 -8 10 -10 10 200 10 600 Operating current (for I/O) ICCIO VddIO = 3.5V, VddIN = 1.5V, MASTERCLK=100MHz PClock = 200MHz Load=25pF 160 mA (*1) All input and input-mode bidirectional pins except PCI interface signals (*2) ACE*, ACK*, BUSSPRT*, BWE[3:0]*, CE[7:0]*, DMAACK[3:0], DMADONE*, EEPROM_CS, EEPROM_DO, EEPROM_SK, HALTDOZE, PIO[7:0], RTS[1:0], SWE*, SYSCLK, TIMER[1:0], TXD[1:0] (*3) DCLK, PCST[8:0], TDO, TPC[3:1] (*4) Applies to ADDR[19:0], CAS*, CB[7:0], CKE, DATA[63:0], DQM[7:0], OE*, RAS*, SDCLK[3:0], SDCLKIN, SDCS[3:0]* and WE when an output buffer drive strength of 16 mA is used. (*5) Drive 8mA: ADDR[19:0], CAS*, CB[7:0], CKE, DATA[63:0], DQM[7:0], OE*, RAS*, SDCLK[3:0], SDCLKIN, SDCS[3:0]*, WE (*6) EEPROM_DI, CGRESET*, RESET*, TRST*, BYPASSPLL*, MASTERCLK, DMADONE*, PIO[7:0], SDCLKIN (*7) CTS[1:0]*, DMAREQ[3:0], RXD[1:0], SCLK, TCLK, INT[5:0], TCK, TDI, TEST[4:0]*, TMS, ACK*, CB[7:0], DATA[63:0], ADDR[19:0], NMI* (*8) (*6), (*7) Signals except for TRST* (*9) TRST* (*10) TXD[1:0] EJC-TMPR4927ATB-28 17 / Jan / 02 TOSHIBA CORPORATION INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 DC Characteristics except for PCI interface (Tc = 0 ~ 70C, VddIO = 3.3V 0.2V, VddIN = 1.5V 0.1V, Vss = 0V) PARAMETER Low-level input voltage High-level input voltage High-level output voltage Low-level output voltage Input leakage current Hi-z output leakage current SYM VILPCI VIHPCI VOHPCI VOLPCI IIHPCI IILPCI IOZPCI CONDITIONS (*1) (*1) (*2) IOUT = -500uA (*2) IOUT = 1500uA 0 < VIN < VddIO (*3) MIN. -0.5 1.8 VddIO x 0.9 -10 -10 -10 MAX. 0.9 VddIO+0.3 VddIO x 0.1 10 10 10 UNIT V V V V A A A (*1) ID_SEL, PCICLKIN, C_BE[3:0], DEVSEL*, FRAME*, GNT[3:0]*, IRDY*, LOCK*, M66EN, PAR, PCIAD[31:0], PERR*, REQ[3:0], SERR*, STOP*, TRDY* (*2) ID_SEL, PCICLKIN (*3) PCICLK[5:0], PME* Power circuit for PLL Recommended circuit for PLL TX4927 VddIN VddIN L C3 C2 R PLL2Vdd_A PLL1Vdd_A R L C3 C1 PLL2Vss_A PLL1Vss_A C1 C2 L R Vss Vss R L Note) C1, CS, C3, R and L should be placed as closed to the processor as possible. PARAMETER Resistor Inductance Capacitor SYMBOL R L C1 C2 C3 AS a reference Value 5 T.B.D. 1 82 10 1.5V 0.1V UNIT ohm H nF nF F V VddIN, PLL1Vdd_A, PLL2Vdd_A EJC-TMPR4927ATB-29 17 / Jan / 02 TOSHIBA CORPORATION INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 5.5 AC CHARACTERISTICS MASTERCLK AC Characteristics (Tc = 0 ~ 70C, VddIO = 3.3V 0.2V, VddIN = 1.5V 0.1V, VSS = 0V) PARAMETER MASTERCLK Period MASTERCLK Frequency (*1) MASTERCLK High MASTERCLK Low Internal Operating Frequency MASTERCLK Rise Time MASTERCLK Fall Time SYM tMCP fMCK tMCH tMCL fcpu tMCR tMCF CONDITION ADDR[2]=H in boot time ADDR[2]=H in boot time MIN. 10 12.5 3 3 50 MAX. 80 100 UNIT ns MHz ns ns 200 2 2 MHz ns ns (*1) Proper circuit operation of the TX4927 is guaranteed only when power supply to it is stable and the on-chip PLL is enabled. tMCP tMCL tMCH MASTERCLK 0.8 VddIO 0.2 VddIO tMCR Power On AC Characteristics tMCF (Tc = 0 ~ 70C, VddIO = 3.3V 0.2V, VddIN = 1.5V 0.1V, VSS = 0V) PARAMETER PLL stable time CGRESET* width time RESET* width time SYM tMCP_PLL tMCK_PLL tMCH_PLL CONDITION MIN. 10 1 1 MAX. UNIT ms ms - ms VddIN, VddIO, PLL1Vdd_A, PLL2Vdd_A MASTERCLK stable time MASTERCLK t MCP_PLL CGRESET * t MCK_PLL tMCH_PLL RESET * EJC-TMPR4927ATB-30 17 / Jan / 02 TOSHIBA CORPORATION INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 SDRAM Interface AC Characteristics (Tc = 0 ~ 70C, VddIO = 3.3V 0.2V, VddIN = 1.5V 0.1V, VSS = 0V) Signal Name SDCLK[3:0] I/O O Load (pF) 50 Buffer Type 16mA SYM Tcyc_sdclk Thigh_sdclk Tlow_sdclk Tbp Tval_addr1 Tval_sdcs Tval_ras Tval_cas Tval_we Tval_cke Tval_dqm Tval_data1 Tval_data1v Tval_data1z Tsu_data1b Th_data1b Tsu_data1n b Th_data1nb Descriptions Clock Cycle Time Clock High Time Clock Low Time Clock Input Timing ( Non bypass mode ) Address Output Delay (*1) Output Delay for Chip Select Output Delay for RAS* (*1) Output Delay for CAS* (2 Cycle Bus Operation) Output Delay for Write Enable (2 Cycle Bus Operation) Output Delay for Clock Enable Output Delay for Data Mask (*1) Output Delay for Data (High <->low) (*1) Output Delay for Data (Hi-Z -> valid) Output Delay for Data (valid->Hi-Z) Data Setup Time (Bypass mode) Data Hold Time (Bypass mode) Data Setup Time (Non bypass mode) Data Hold Time (Non bypass mode) MIN (ns) 10 3 3 0 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 4.0 0.5 1.5 1.0 MAX (ns) 4.0 6.5 6.5 6.5 6.5 6.5 6.5 6.5 6.5 6.5 6.5 - SDCLKIN ADDR[19:5] SDCS[3:0]* RAS* CAS* WE* CKE DQM[7:0] DATA[63:0] I O O O O O O O I/O 150 100 150 150 150 150 50 50 16mA 16mA 16mA 16mA 16mA 16mA 16mA 16mA - - (*1) An SDRAM bus transaction can complete in no more than two clock cycles through programming the SDRAMC and Configuration registers. EJC-TMPR4927ATB-31 17 / Jan / 02 TOSHIBA CORPORATION INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 SDCLK Tval_* OUTPUT Tsu_* INPUT inputs valid Th_* outputs valid Output Signals and when bypass mode input Signals (SDCLK basis) SDCLK Tbp SDCLKIN Tsu_* INPUT inputs valid Th_* When non bypass mode input signals (SDCLK basis) EJC-TMPR4927ATB-32 17 / Jan / 02 TOSHIBA CORPORATION INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 External Bus Interface AC Characteristics (Tc = 0 ~ 70C, VddIO = 3.3V 0.2V, VddIN = 1.5V 0.1V, VSS = 0V) Signal Name SYSCLK I/O O Load (pF) 50 Buffer Type 8mA(fix) SYM Tcyc_sysclk Thigh_sysclk Tlow_sysclk Tval_addr2 Tval_ce Tval_oe Tval_swe Tval_bwe Tval_ace Tval_bus Tval_data2 Tval_data2v Tval_data2z Tsu_data2 Th_data2 Tval_ack Tval_ackv Tval_ackz Tsu_ack Th_ack Descriptions Clock Cycle Time Clock High Time Clock Low Time Output Delay for Address Output Delay for Chip Enable Output Delay for Output Enable Output Delay for Write Enable Output Delay for Byte Enable Output Delay for Address Clock Enable Output Delay for Bus Separate Output Delay for Data (High <-> Low) Output Delay for Data (Hi-Z -> valid) Output Delay for Data (valid -> Hi-Z) Data Setup Time Data Hold Time Output Delay for ACK* (High <-> Low) Output Delay for ACK* (Hi-Z -> valid) Output Delay for ACK* ( valid -> Hi-Z) ACK* Setup Time ACK* Hold Time MIN (ns) 10 4 4 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 6.0 0.5 1.5 1.5 1.5 6.0 0.5 MAX (ns) 6.5 8.5 8.5 8.5 8.5 8.5 8.5 6.5 8.5 8.5 8.5 6.5 8.5 - ADDR[19:5] CE[7:0]* OE* SWE* BWE*[3:0] ACE* BUSSPRT* DATA[31:0] O O O O O O O I/O 150 50 50 50 50 50 50 50 16mA 8mA(fix) 8mA(fix) 8mA(fix) 8mA(fix) 8mA(fix) 8mA(fix) 16mA ACK* I/O 50 8mA(fix) - - Tcyc_sysclk Thigh_sysclk Tlow_sysclk SYSCLK Tval_* OUTPUT Tsu_* Th_* outputs valid INPUT inputs valid External Bus Interface EJC-TMPR4927ATB-33 17 / Jan / 02 TOSHIBA CORPORATION INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 PCI Interface AC Characteristics Signal Name PCICLKIN I/O I PCI-bus Load Spec. 66MHz (pF) SYM Tcyc66 Thigh66 Tlow66 Tslew66 33MHz Tcyc33 Thigh33 Tlow33 Tslew33 PCICLK[5:0] O 66MHz 50 Tcyco66 Thigho66 Tlowo66 33MHz 70 Tcyco33 Thigho33 Tlowo33 PCIAD[31:0] C_BE[3:0] PAR FRAME* IRDY* TRDY* STOP* DEVSEL* PERR* SERR* LOCK* M66EN PME* ID_SEL REQ[3:0]* GNT[3:0]* I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O3 I I/O I/O 66MHz 50 30 33MHz 70 Tskw Tval66 Tsu66 Th66 Tval33 Tsu33 Th33 Descriptions Input Clock Cycle Time Input Clock High Time Input Clock Low Time Input Clock Through rate [V/ns] Input Clock Cycle Time Input Clock High Time Input Clock Low Time Input Clock Through rate [V/ns] Output Clock Cycle Time Output Clock High Time Output Clock Low Time Output Clock Cycle Time Output Clock High Time Output Clock Low Time Output Clock Slew (point to point connection) Output Delay (bus connection) Setup Time (bus connection) Hold Time (bus connection) Output Delay (bus connection) Setup Time (bus connection) Hold Time (bus connection) MIN (ns) 15 6 6 1.5 30 11 11 1 15 6 6 30 11 11 0 2 3 (TBD) 0.5 2 5 0 MAX (ns) 30 4 40 4 30 40 TBD 8 8 - 66MHz 30 - Tppd66 Tpps66 Tpph66 Tppd33 Tpps33 Tpph33 Output Delay (point to point connection) Setup Time (point to point connection) Hold Time (point to point connection) Output Delay (point to point connection) Setup Time (point to point connection) Hold Time (point to point connection) 2 7 0.5 2 10 0 11 12 - 33MHz 70 - EJC-TMPR4927ATB-34 17 / Jan / 02 TOSHIBA CORPORATION INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 Tcyc66/Tcyc33 Thigh66/Thigh33 0.6 Vcc 0.5 Vcc 0.4 Vcc 0.3 Vcc 0.2 Vcc (Vcc=3.3V) PCICLKIN Tlow66/Tlow33 Tslew66/Tslew33 0.4 Vcc p-to-p (minimum) Tsu66/Tsu33/Tpps66/Tpps33 Th66/Th33/Tpph66/Tpph33 INPUT inputs valid Tval66/Tval33/Tppd66/Tppd33 OUTPUT outputs valid PCI Interface (3.3V) Tcyco66/Tcyco33 Thigho66/Thigho33 Tlowo66/Tlowo33 PCICLK[n] Tskw PCICLK [except for n] n=0 to 5 PCI Clock Skew EJC-TMPR4927ATB-35 17 / Jan / 02 TOSHIBA CORPORATION INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 6. Package EJC-TMPR4927ATB-36 17 / Jan / 02 TOSHIBA CORPORATION INTEGRATED CIRCUIT TOSHIBA RISC PROCESSOR TMPR4927ATB-200 7. HISTORY Modify the description for SDRAM Controller Modify Pin layout Modify from DFS signal to TEST2 signal 13/Jan/01 Added the Package Diagram 22/Jan/01 DC/AC Timing 26/Jan/01 Modify the description 6/Feb/01 Modify the description 20/Aug/01 17/Jan/02 Modify the Signal description and AC Characteristics Modify the product name TMPR4927TB -> TMPR4927ATB-200 Modify the spec of AC and DC 28/Aug/00 EJC-TMPR4927ATB-37 17 / Jan / 02 TOSHIBA CORPORATION |
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